Like erasable programmable read only memory (EPROM) cells, EEPROM cells include floating gates and store data by injecting electrons into the floating gate or erase data by emitting the electrons from the floating gate. However, EEPROMs adopt a manner of injecting or emitting electrons, which is quite different from EPROMs.
In EPROMs, electrons are injected into a floating gate by hot carrier injection (HCI) and emitted from the floating gate by energy of ultraviolet rays irradiated to the floating gate. By comparison, EEPROMs employ tunneling induced by a thin tunnel insulation layer for injecting and emitting electrons. That is, if a strong electric field of about 10 MeV/cm is applied to both surfaces of the tunnel insulation layer, a current flows through the tunnel insulation layer, which is normally called “Fowler-Nordheim (F-N) tunneling”. In the EEPROMs, the F-N tunneling is used for injecting and emitting electrons.
In the case of the EEPROMs such as FLOTOX-type memories, a single memory cell includes a pair of transistors, which are connected in a series. One is a selection transistor for selecting cells, and the other is a memory transistor for storing data. The memory transistor includes a floating gate for storing electric charge, a control gate electrode for controlling a memory transistor, and a gate interlayer dielectric layer interposed therebetween.
FIGS. 1 through 3 are cross-sectional views for illustrating a method of fabricating a conventional nonvolatile memory device.
Referring to FIG. 1, a gate insulation layer 102 is formed on a semiconductor substrate 100, and a channel diffusion layer 110 is formed in a predetermined region of the semiconductor substrate 100. Although not shown in the drawings, before forming the gate insulation layer 102, a device isolation layer is formed at a predetermined region of the semiconductor substrate to define an active region. The gate insulation layer 102 is formed on the active region. A portion of the gate insulation layer 102 is removed to expose a predetermined region of the channel diffusion layer 110. A tunnel insulation layer 118 is formed on the exposed region. That is, the tunnel insulation layer 118 is disposed on the channel diffusion layer 110. A lower conductive layer and a dielectric layer are sequentially formed on an entire surface of the semiconductor substrate 100. Thereafter, the lower conductive layer and the dielectric layer are successively patterned to form a floating gate pattern 120a covering the channel diffusion layer 110, and a lower selection gate pattern 120b separated from the floating gate pattern 120a by a predetermined space. A gate interlayer dielectric layer 122a is formed on the floating gate pattern 120a, and an interlayer dielectric pattern 122b is formed on the lower selection gate pattern 120b. 
Referring to FIG. 2, a thermal process is performed on the resultant structure to form a sidewall insulation layer 124 on sidewalls of the floating gate pattern 120a and the lower selection gate pattern 120b. An upper conductive layer 126 is formed on an entire surface of the resultant structure where the sidewall insulation layer 124 is formed.
Referring to FIG. 3, the upper conductive layer 126 is patterned to form a control gate electrode 126a on the gate interlayer dielectric layer 122a and at the same time form an upper selection gate 126b on the interlayer dielectric pattern 122b. 
Although not shown in the drawings, in another method, after forming the lower conductive layer, the upper conductive layer, the dielectric layer, and the lower conductive layer may be successively patterned to form a control gate electrode as well as a gate interlayer dielectric pattern and a floating gate pattern, which are self-aligned to the control gate electrode. At the same time, an upper selection gate as well as an interlayer dielectric pattern and a lower selection gate pattern, which are self-aligned to the upper selection gate, may be formed.
The floating gate pattern 120a, the gate interlayer dielectric layer 122a, and the control gate electrode 126a constitute a gate pattern of the memory transistor. The lower selection gate pattern 120b, the interlayer dielectric pattern 122b, and the upper selection gate 126b constitute a gate pattern of the selection transistor.
Next, impurities are injected into the semiconductor substrate between the memory gate pattern and the selection gate pattern to form a channel region 110a including the channel diffusion layer 110. A source region 108 is formed in the semiconductor substrate adjacent to the memory gate pattern. A drain region 112 is formed in the semiconductor substrate adjacent to the selection gate pattern.
FIG. 4 is a cross-sectional view for illustrating disadvantages of the conventional nonvolatile memory device. Referring to FIG. 4, a cell array of the nonvolatile memory device of FLOTOX type includes memory cells, each of which has a selection transistor and a memory transistor. In the foregoing cell array, adjacent memory cells are disposed symmetrically with respect to each other. That is, each memory cell has a source region in common with a memory cell adjacent to one side thereof, and has a drain region in common with a memory cell adjacent to the other side thereof. Accordingly, when the floating gate pattern 120a and the lower selection gate pattern 120b are formed to be misaligned, spaces between the source regions 108 and the channel regions 110a become irregular. This may cause dispersion of threshold voltages of memory transistors to be increased.